Jeff,
I have a feeling you're talking about this section:
> pci_write_config_byte (pdev, PCI_CACHE_LINE_SIZE, cls);
> pci_read_config_word (pdev, PCI_COMMAND, &pcr);
>
> /* Turn off Fast B2B enable */
> pcr &= ~PCI_COMMAND_FAST_BACK;
> /* Turn on SERR# enable and others */
> pcr |= (PCI_COMMAND_SERR | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
> PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
>
> pci_write_config_word (pdev, PCI_COMMAND, pcr);
> pci_read_config_word (pdev, PCI_COMMAND, &pcr);
Basically, this section exists from a time when I had no idea why the
card was behaving badly, so I was trying everything :-).
So, after revisiting them, I see that setting cache line size to 0 and
then using memory write and invalidate doesn't make any sense. I'm thinking
both can just be dropped, since I haven't seen any change in performance on
the machines I've made netperf runs with (a constant 14.7 Mb/s) after
changing these.
Any thoughts?
Kent
Thus Spake Jeff Garzik:
>Sorry I've been slow to respond... I'm going to apply your driver
>locally, so you and I have a good baseline to work with, but there are
>some small issues related to PCI initialization that I want to review
>and discuss with you, before submitting officially to Marcelo...
>
>(another message should follow during the upcoming work week)
>
>Regards,
>
> Jeff
>
>
>
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This archive was generated by hypermail 2b29 : Thu Mar 07 2002 - 21:00:34 EST