There seem to be a problem with PPC, you didn't put back the
PPC405_ERR77 macro in your new implementation. That means you
may hit a PPC 405gp CPU bugs and lose atomicity of lwarx/stwcx.
+#define __HAVE_ARCH_UPDATE_COUNT
+static inline int __update_count(atomic_t *count, int incr)
+{
+ int old_count, tmp;
+
+ __asm__ __volatile__("\n"
+"1: lwarx %0,0,%3\n"
+" srawi %1,%0,31\n"
+" andc %1,%0,%1\n"
+" add %1,%1,%4\n"
++ PPC405_ERR77(0,%3)
+" stwcx. %1,0,%3\n"
+" bne 1b"
+ : "=&r" (old_count), "=&r" (tmp), "=m" (*count)
+ : "r" (count), "r" (incr), "m" (*count)
+ : "cc");
Ben.
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This archive was generated by hypermail 2b29 : Thu Mar 07 2002 - 21:00:15 EST