>
>> For #6, the udelay(1) had more to do with the following write() than
>> with spin_lock(). When that delay was not there, the write failed
>> randomly. The same with the udelay(10) at the end of the interrupt
>> function...
>
>That smells of covering up a race rather than fixing something. Another
>thing you may be doing perhaps is hiding PCI posting effects ?
Ok, I thought of one thing that might make things clearer here: when I
say "the write failed", I mean that we saw the write go out on the PCI bus
and then the box locked up. We were looking at it on a PCI bus analyzer.
That, and it wasn't just this write, or just writes in general, it really
seemed random.
BTW, I don't know what PCI posting effects are...
Kent
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This archive was generated by hypermail 2b29 : Wed Jan 23 2002 - 21:00:30 EST