how is processor cache coherency maintained for device drivers

From: Christopher Friesen (cfriesen@nortelnetworks.com)
Date: Fri Nov 09 2001 - 16:46:18 EST

I'm trying to help track down some infrequent and difficult to reproduce pci bus
parity errors that we're seeing on a cPCI card, and one of the things that has
been suggested is that it may have something to do with DMA coherency between
devices and the processor.

Can someone point me to the proper code/information that deals with how the
processor knows that the memory corresponding to the ethernet device is no
longer up-to-date? Is it somehow marked as non-cacheable, or is it snooped,
explicitly flushed, or what?

The platform in question is a Motorola MCPN765 card, with a PPC7400 processor,
running a modified 2.2.17 kernel.

Thanks,

Chris 

-- 
Chris Friesen                    | MailStop: 043/33/F10  
Nortel Networks                  | work: (613) 765-0557
3500 Carling Avenue              | fax:  (613) 765-2986
Nepean, ON K2H 8E9 Canada        | email: cfriesen@nortelnetworks.com
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This archive was generated by hypermail 2b29 : Thu Nov 15 2001 - 21:00:23 EST