Hi,
I am confused about Intel's documentation regarding PAE. When PAE is
enabled, CR3 contains a few flags (write-through and cache disabled), 3
reserved bits, and - and here is my confusion - a 27-bit
page-directory-pointer-table base address field, "providing the 27 most
significant bits of the physical address of the PDPT, which forces the
table to be located on a 32-byte boundary."
Now, in PAE, the physical address is a 36-bit value. If we take off 27
bits, there are 9 bits left, forcing the table to be located on a
512-byte boundary.
Is this correct, or do the 27-bits present the bits 6..31 of the
physical address, forcing the table to be located on a 32-byte boundary
AND below 4GB (physical)?
Camiel.
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This archive was generated by hypermail 2b29 : Fri Sep 07 2001 - 21:00:13 EST