Richard Gooch proclaimed:
> Er, are you sure about this? The problem isn't the size of your cache,
> it's the size of your TAG RAM. That's a different beast.
Cachable memory area is a function of cache size, tag size and cache
mode (wb or wt - first needs dirty tag, second doesn't). With VIA MVP3
boards for example, cachable memory depends on the size of the cache.
Which is why most of the boards with this chipset had 1 MB level 2 cache
(enough for 128 mb with writeback or 256 mb with writethrough), some
even had 2 MB (for twice that).
Holger
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Fri Aug 31 2001 - 21:00:29 EST