At 12:03 PM -0700 2001-06-14, David S. Miller wrote:
>Jonathan Lundell writes:
> > As I recall, even a midline chipset such as the ServerWorks LE
> > supports the use of two north bridges, which implies two PCI bus
> > domains.
>
>It hides this fact by making config space accesses respond in such a
>way that it appears that it is all behind one PCI controller. The
>BIOS even avoids allowing any of the MEM and I/O resources from
>overlapping.
So we end up with a single domain and max 256 buses. Still, it's not
behavior one can count on. Sun's U2P PCI controller certainly creates
a new PCI domain for each controller. It's easier in architectures
other than IA32, in a way, since they typically don't have the 64KB
IO-space addressing limitation that makes heavily bridged systems
problematical on IA32 (one tends to run out of IO space).
-- /Jonathan Lundell. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Fri Jun 15 2001 - 21:00:23 EST