>>>>> "Gérard" == Gérard Roudier <groudier@club-internet.fr> writes:
Gérard> On Fri, 9 Feb 2001, Alan Cox wrote:
>> DMA to main memory normally invalidates those lines in the CPU
>> cache rather than the cache snooping and updating its view of them.
Gérard> In PCI, it is the Memory Write and Invalidate PCI transaction
Gérard> that is intended to allow core-logics to optimize DMA this
Gérard> way. For normal Memory Write PCI transactions or when the
Gérard> core-logic is aliasing MWI to MW, the snooping may well
Gérard> happen. All that stuff, very probably, varies a lot depending
Gérard> on the core-logic.
In fact one has to look out for this and disable the feature in some
cases. On the acenic not disabling Memory Write and Invalidate costs
~20% on performance on some systems.
Jes
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This archive was generated by hypermail 2b29 : Thu Feb 15 2001 - 21:00:19 EST