davej@suse.de wrote:
>
> > There are tests for all this in the feature flags for intel and
> > non-intel CPUs like AMD -- including MTRR settings. All of this could
> > be dynamic. Here's some code that does this, and it's similiar to
> > NetWare. It detexts CPU type, feature flags, special instructions,
> > etc. All of this on x86 could be dynamically detected.
>
> Detecting the CPU isn't the issue (we already do all this), it's what to
> do when you've figured out what the CPU is. Show me code that can
> dynamically adjust the alignment of the routines/variables/structs
> dependant upon cacheline size.
If the compiler always aligned all functions and data on 16 byte
boundries (NetWare)
for all i386 code, it would run a lot faster. Cache line alignment
could be an option in the loader .... after all, it's hte loader that
locates data in memory. If Linux were PE based, relocation logic would
be a snap with this model (like NT).
Jeff
>
> regards,
>
> Davej.
>
> --
> | Dave Jones <davej@suse.de> http://www.suse.de/~davej
> | SuSE Labs
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