On Sun, Oct 15, 2000 at 11:35:23PM +0100, Kenn Humborg wrote:
> We've kind of got 1.5-level page tables. There are actually 3 page tables.
> The system page table maps memory starting at 0x80000000. The P0 process
> page table maps from 0x0 up and the P1 process page table maps from
> 0x7fffffff down.
>
> This means that sparse address spaces are going to be _really_ expensive
> on PTEs. I don't know how much of a problem this is going to be yet,
> but I'm sure it's going to be fun :-)
Can you put the flat page table array into virtual memory? On MIPS and a
few other RISCs doing software tlb refills it's the machanism of choice
for performance reasons but it could just as well be used to safe memory.
Ralf
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