On Fri, 29 Sep 2000, Keir Fraser wrote:
> > Is it really necessary to use one of the event counters ? this means
> > those of us using event counters from modules can't use this oopser at
> > the same time, which is a pity.
> Indeed. What was wrong with the existing method, where you route an
> external timer in AEOI mode through LVT0? Is it inefficient, or known
> to fail on some boards, or something like that?
it needs an existing IOAPIC chip, which is not present in the majority of
single-processor systems.
what is wrong with clearing the first performance counter before using it?
The NMI oopser is completely nonintrusive.
so on UP systems you'll have to choose between the NMI oopser and other
uses of the first counter. You can save/restore the contents of the first
counter if you want to reactivate the NMI oopser. This is all user-space
policy, the kernel doesnt mind.
> Another question relating to the setup of local APICs on current
> -testX kernels: how are external interrupts routed through to the
> processor? [...]
they are delivered by the IOAPIC, to one (or more) of the local APICs via
the APIC bus, the local APIC then (after IRQ arbitration) interrupts the
CPU core.
Ingo
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This archive was generated by hypermail 2b29 : Sat Sep 30 2000 - 21:00:24 EST