RE: Cache coherency... and locking

From: Oliver Xymoron (oxymoron@waste.org)
Date: Fri Jul 21 2000 - 10:50:16 EST


On Fri, 21 Jul 2000, Oliver Xymoron wrote:

> > You say we are 'assuming' writes show up in the order performed,
> > that implies it may not be true?
>
> True for all the processors we're currently working with. Linus talks
> about assuming a 'sane architecture' as the common core and making ports
> minimal variations from that. Currently write ordering is one of those
> things considered sane.

Retraction time - Manfred's right, we don't generally assume write
ordering on SMP. Writes remain ordered on single processors (ie reads
never speculate ahead of writes) but that's fairly obviously the only sane
way to go. x86 is strongly ordered but other systems and things like PCI
bus are not necessarily.

It's best not to think about subtle things like causality models at 2am.

--
 "Love the dolphins," she advised him. "Write by W.A.S.T.E.." 

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