Richard B. Johnson writes:
> A 33MHz, 32-bit Revision 2.2-compliant PCI bus gives you 132 MB/second.
> That's the spec. There is no way to slow it down except by a disconnect.
Can we be more precise here please? 132MB/s is not realistic if you're
talking about most PCI shared memory implementations.
Yes, its true that you might be able to achieve nearly full bandwidth when
accessing ///prefetchable/// PCI memory, but most shared PCI memory is not
prefetchable.
"Prefetchable" means that the bridges can pull much data across the PCI
bus and cache it, so that the next read does not cause a PCI transaction
(eg, only one in 8 reads causes a transaction, but this depends on the
setup).
As I say, for a lot of shared PCI memory stuff (eg, network cards, some video
cards), the memory regions are not "Prefetchable". This means that for every
read by the CPU, a PCI transaction must be made. One PCI transaction from
start to finish takes at least 4 clocks (Req, Frame, Data, Disconnect). You
may also have arbitration delays as well, which will further reduce the
available bandwidth.
In total, this means for the non-prefetchable shared PCI memory bandwidth
is at the most 33MB/s on a 32-bit PCI bus running at 33MB/s.
_____
|_____| ------------------------------------------------- ---+---+-
| | Russell King rmk@arm.linux.org.uk --- ---
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This archive was generated by hypermail 2b29 : Thu Jun 15 2000 - 21:00:32 EST