On Tue, 23 May 2000, Jamie Lokier wrote:
> Linus Torvalds wrote:
> > [ You _really_ don't want to know about taking page faults in the middle
> > of a task switch that is the result of a task gate being used to handle
> > another page fault, which in turn happened while we were loading the
> > second part of a page-crossing 32-bit word. Question: do you mark the
> > page table entry for the incomplete part that you already checked as
> > accessed or not? ]
>
> Actually, I do want to know. (I'm writing an x86 formal spec).
> Do you mark the pte? :-)
It actually depends on the CPU, and the type of access.
If it's a "atomic" 32-bit access, you don't mark the PTE accessed, because
the page fault will have been noticed before any data was actually
fetched. But that is not true for some data that has more "structure" to
it that can be loaded as separate pieces and then a page fault part-way
through can have already set some of the accessed bits.
The reason it is CPU-dependent seems to be that with speculative loads and
out-of-order execution the whole thing becomes much more subtle, and
"separate pieces" is no longer the firm thing it used to be. A Pentium
core will act differently from a PPro core in many of these special cases.
Nobody sane obviously should ever care. It's hard to even test for, in
many cases. We have some rather insane tests, and there's a number of
differences between different chips.
Note that many of these things aren't even documented to work. Intel
explicitly documents that if you use task switching hardware the TSS
should all be on a single page etc. And nobody uses the hardware any more
now that even Linux does it all in software. But it's often more painful
to be different and have to convince everybody that those differences do
not matter than to just try to look exactly like everybody else as far as
humanly possible.
Linus
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This archive was generated by hypermail 2b29 : Tue May 23 2000 - 21:00:24 EST