Hi!
> Assume you only have 2 pages of Physical memory (P0 and P1). Replacement policy is
> LRU (Least Recently Used). No pages are in memory at the start, but P1 was LRU.
> Show the Paging activity for a 32-bit word at offset 0x3fe in
> both source and destination pages:
>
> T P0 P1
> ------------------
> 0 X X
> 1 V0 X
> 2 V0 V1 ;instruction loaded and decoded -- it stays in
> the CPU now **
CPU's don't work like that. Page fault means potentially
context-switch, and there's _no_ place for information "where in the
middle of instruction are we" in TSS.
> 3 V2 V1 ;load first source page
> 4 V2 V4 ;load first dest. page and copy 1st byte
> 5 V2 V4 ;copy 2nd byte (pages are already in memory
> 6 V3 V4 ;load 2nd source page
> 7 V3 V5 ;load 2nd dest page and copy 3rd byte
> 8 V3 V5 ;4th byte is copied.
And they will not interrupt one mosvd operation like this!
Pavel
-- The best software in life is free (not shareware)! Pavel GCM d? s-: !g p?:+ au- a--@ w+ v- C++@ UL+++ L++ N++ E++ W--- M- Y- R+- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
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