In message <20000117163454.S11300@thepuffingroup.com>, Matthew Wilcox writes:
>On Mon, Jan 17, 2000 at 01:18:45PM -0800, David S. Miller wrote:
>> > If the intention is to clear bit 31, `&= 0x7fffffff' is the thing which
>> > works and is probably more efficient.
>>
>> Not true on all RISC machines I am familiar with. It's 2 instructions
>> either way. On x86 you'll end up using a larger opcode and one of
>> x86's most notable performance advantages is it's code density.
>
>Really? On ARM and PA-RISC, it's 1 instruction (BIC and DEPI,
>respectively). Do SPARC, MIPS and Alpha really not have a `clear bit'
>instruction?
GCC on ARM will actually generate a BIC instruction for code containing the
two shifts in any case, so the point is perhaps a moot one.
p.
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