Re: [PATCH] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[Dmitry Baryshkov]

On Mon, Mar 02, 2026 at 11:42:32PM +0530, Akhil P Oommen wrote:
> On 3/1/2026 12:03 AM, Dmitry Baryshkov wrote:
> > Due to the way the DDR controller is organized on Glymur, hardware
> > engineers strongly recommended disabling UBWC bank swizzling on Glymur.
> > Follow that recommendation.
> > 
> > Fixes: 9b21c3bd2480 ("soc: qcom: ubwc: Add configuration Glymur platform")
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> > ---
> >  drivers/soc/qcom/ubwc_config.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> > index 1c25aaf55e52..31e0d55c6d9e 100644
> > --- a/drivers/soc/qcom/ubwc_config.c
> > +++ b/drivers/soc/qcom/ubwc_config.c
> > @@ -231,8 +231,7 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
> >  static const struct qcom_ubwc_cfg_data glymur_data = {
> >  	.ubwc_enc_version = UBWC_5_0,
> >  	.ubwc_dec_version = UBWC_5_0,
> > -	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> > -			UBWC_SWIZZLE_ENABLE_LVL3,
> > +	.ubwc_swizzle = 0;
> >  	.ubwc_bank_spread = true,
> >  	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
> >  	.highest_bank_bit = 16,
> 
> Reviewed-by: Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx>
> 
> We need a fix on the gpu side to properly handle this case. I will post
> a patch.

Ack.


-- 
With best wishes
Dmitry