Re: [PATCH 1/3] clk: amlogic: Fix out-of-range PLL frequency setting

[Chuan Liu]

Hi Jerome,
Thanks for your review.


On 10/22/2025 7:57 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed 22 Oct 2025 at 14:58, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@xxxxxxxxxx> wrote:
>
> > From: Chuan Liu <chuan.liu@xxxxxxxxxxx>
> >
> > meson_clk_get_pll_range_index incorrectly determines the maximum value
> > of 'm'.
>
> This explanation is little light !
>
> How did the problem show up ? Under which condition ? How did you come
> this conclusion ?

In actual use cases, we haven't encountered any issues caused by this,
because we ensure that range->max <= (1 << pll->m.width) when
configuring the range.

If the calculated 'm' falls into the range:
- range->max < m < (1 << pll->m.width)
An incorrect 'm' value may be selected here. Therefore, comparing
against range->max is more appropriate in this case.

> Other people having problems might benefit from the explanation
>
> > Fixes: 8eed1db1adec6 ("clk: meson: pll: update driver for the g12a")
> > Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx>
> > ---
> >   drivers/clk/meson/clk-pll.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> > index 1ea6579a760f..b07e1eb19d12 100644
> > --- a/drivers/clk/meson/clk-pll.c
> > +++ b/drivers/clk/meson/clk-pll.c
> > @@ -191,7 +191,7 @@ static int meson_clk_get_pll_range_index(unsigned long rate,
> >        *m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
> >
> >        /* the pre-divider gives a multiplier too big - stop */
> > -     if (*m >= (1 << pll->m.width))
> > +     if (*m > pll->range->max)
>
> Making sure m does not exceed the maximum value is valid too.
> You should check both conditions then

Ok, fix it in the next version.

> >                return -EINVAL;
> >
> >        return 0;
>
> --
> Jerome