Re: [PATCH 2/4] iio: adc: Add support for the Renesas RZ/N1 ADC

[Herve Codina]

Hi Wolfram,

On Fri, 17 Oct 2025 08:28:16 +0200
Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:

> Hi Herve,
> 
> On Wed, Oct 15, 2025 at 04:28:14PM +0200, Herve Codina (Schneider Electric) wrote:
> > The Renesas RZ/N1 ADC controller is the ADC controller available in the
> > Renesas RZ/N1 SoCs family. It can use up to two internal ACD cores (ADC1  
> 
> ADC cores

Yes, indeed.

> 
> > and ADC2) those internal cores are not directly accessed but are handled
> > through ADC controller virtual channels.
> > 
> > Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@xxxxxxxxxxx>  
> 
> Very high level review.
> 
> > +/*                  ADC1 ADC2
> > + * RZ/N1D, BGA 400   y    y
> > + * RZ/N1D, BGA 324   y    n
> > + * RZ/N1S, BGA 324   y    n
> > + * RZ/N1S, BGA 196   y    n
> > + * RZ/N1L, BGA 196   y    n
> > + */  
> 
> I think this table can go. N1D is the only variant supported by Linux
> because others have no SDRAM controller. Maybe a comment after the
> copyright is helpful stating that the second ADC core is utilized when
> the adc2-* bindings are supplied?

Yes, with only RZ/N1D supported, this table doesn't bring any additional
information.

As you suggested, I will add information about ADC cores in the header
part of this .c file.

> 
> > +static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
> > +					 int adc1_ch, int adc2_ch)
> > +{
> > +	u32 vc = 0;
> > +
> > +	if (adc1_ch != -1)
> > +		vc |= RZN1_ADC_VC_ADC1_ENABLE | RZN1_ADC_VC_ADC1_CHANNEL_SEL(adc1_ch);
> > +
> > +	if (adc2_ch != -1)
> > +		vc |= RZN1_ADC_VC_ADC2_ENABLE | RZN1_ADC_VC_ADC2_CHANNEL_SEL(adc2_ch);  
> 
> Are you open to either use an errno (maybe EACCES) or define something
> custom (maybe RZN1_ADC_NO_CHANNEL) instead of hardcoded -1? I think I
> like the latter a tad more.

I prefer RZN1_ADC_NO_CHANNEL too instead of an error code and I will use
that instead of -1 in the next iteration.

Best regards,
Hervé