Re: [PATCH net-next v13 00/12] Add Microchip ZL3073x support (part 1)

[Jiri Pirko]

Fri, Jul 04, 2025 at 08:21:50PM +0200, ivecera@xxxxxxxxxx wrote:
>Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
>provides DPLL and PTP functionality. This series bring first part
>that adds the core functionality and basic DPLL support.
>
>The next part of the series will bring additional DPLL functionality
>like eSync support, phase offset and frequency offset reporting and
>phase adjustments.
>
>Testing was done by myself and by Prathosh Satish on Microchip EDS2
>development board with ZL30732 DPLL chip connected over I2C bus.
>
>---
>Changelog:
>v13:
>* added support for u64 devlink parameters
>* added support for generic devlink parameter 'clock_id'
>* several patches squashed into one per @jpirko's advice
>* renamed devlink version 'cfg.custom_ver' to 'custom_cfg'
>* per discussion with @jpirko, the clock_id is now generated randomly
>  and user have an option to change it via devlink
>* implemented devlink reload to apply clock_id change
>
>v12:
>* Using 'return dev_err_probe()'
>* Separate zl3073x_chip_info structures instead of array
>* Use mul_u64_u32_div() to compute input reference frequency to avoid
>  potential overflow
>* Removed superfluous check in zl3073x_dpll_output_pin_frequency_set()
>
>v11:
>* Fixed uninitialized 'rc' in error-path in patch 9
>
>v10:
>* Usage of str_enabled_disabled() where possible.
>
>v9:
>After discussion with Jakub Kicinski we agreed that it would be better
>to implement whole functionality in a single driver without touching
>MFD sub-system. Besides touching multiple sub-systems by single device
>there are also some technical issues that are easier resolvable
>in a single driver. Additionally the firmware flashing functionality
>would bring more than 1000 lines of code with previous approach to
>the MFD driver - it is not something the MFD maintainers would like
>to see.
>
>Ivan Vecera (12):
>  dt-bindings: dpll: Add DPLL device and pin
>  dt-bindings: dpll: Add support for Microchip Azurite chip family
>  devlink: Add support for u64 parameters
>  devlink: Add new "clock_id" generic device param
>  dpll: Add basic Microchip ZL3073x support
>  dpll: zl3073x: Fetch invariants during probe
>  dpll: zl3073x: Read DPLL types and pin properties from system firmware
>  dpll: zl3073x: Register DPLL devices and pins
>  dpll: zl3073x: Implement input pin selection in manual mode
>  dpll: zl3073x: Add support to get/set priority on input pins
>  dpll: zl3073x: Implement input pin state setting in automatic mode
>  dpll: zl3073x: Add support to get/set frequency on pins

For the DPLL related code:
Reviewed-by: Jiri Pirko <jiri@xxxxxxxxxx>