mv643xx_eth: Delay required in reading the PHY registers.

[Upakul Barkakaty]

Hi all,

I am using the Marvell ethernet driver[mv643xx_eth]. The function
eth_port_read_smi_reg(), uses a delay in order to wait for the SMI
register to become available.

Does anyone have any clue how much time it actually takes for the SMI
register to become available? Actually I am using an older version of
the driver which does not use the udelay functions in the loops. It
rather has a "for" loop for putting a timeout. Now the gcc-4.3.1
compiler optimizes out the "for" loop. So I need to replace the "for"
loop with a delay function. Now the question is "how much delay would
be appropriate".

Any replies in this regard would be appreciated.

--
Regards,
Upakul Barkakaty
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