The PPC doesn't enforce strong ordering, and the PPC supported WinNT:
601:"loads and stores that miss the cache can be reordered as they arbitrate
for the system bus" (Chapter 4.10 from the PowerPC 601 RISC Microprocessor
603: even speculative write operations that don't "alter the target
location" could occur.
I found no documentation about the Alpha, do you know if the full memory
barriers during spin_unlock() are required? The Alpha supported WinNT, and
_if_ the alpha enforces write ordering, then we could remove this memory
barrier/replace it with a weaker memory barrier.
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