For programming the FCR register there is stated:
FCR bit 0: logic 0 disable xmit and recv fifo
FCR bit 0: logic 1 enable xmit and recv fifo;
THIS BIT MUST BE A LOGIC '1' WHEN OTHER FCR BITS ARE WRITTEN or
they will NOT BE PROGRAMMED.
I found a few spots where the fcr bits were written but without
bit 0 SET in the resulting pattern.
I've checked a couple of spec sheets, and yes, this seems to be right.
The two places FCR_ENABLE isn't set while writing to the FCR register is
where we're trying to clear the FIFO's while resetting the UART, while it
doesn't seem to have made any difference, it would be good to this
Thanks for noticing it.
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