But in the case of a heavy filetransfer, the data will need to hit main
memory, especially if the NIC can bus-master DMA from main memory. The
thing is, in a good system, the HD controller will do BM DMA to main
memory and there should be no need at all for the CPU to touch the data.
DMA in, DMA out. Checksum can be handled by the NIC. Now I'm not mad
enough to claim that direct device<->device I/O is the way to go (which
was discussed here recently :).
I fully agree that a meagre 10 MByte/s (for filling a 100 MBit/s net) is
a tiny load on a massive P2/400 with main memory bandwidths of hundreds of
MB/s. But the issue was scalability mainly.
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