Byte ordering on PCI bus - why is readl on PPC swapping bytes?
Petr Vandrovec Ing. VTEI (VANDROVE@vc.cvut.cz)
Mon, 9 Nov 1998 12:40:21 MET-1
I have one tiny question: It was pointed to me by "Bibek Sahu" that
on Alpha, it is not enough to call ioremap() on pcidev->pci_address,
but that I also have to use readb/l/w (and writeb/l/w) on resulting
But I've found that in include/asm-ppc/io.h, there is writel defined
as out_le32(address, data) :-( But matrox devices (and I need it for
matroxfb) have special "PowerPC" mode in which they swaps bytes from
PCI bus ordering (byte position invariant, bits 7-0 are written to
lowest address, so if you are writting dword, bits 31-24 are passed
to PCI data bits 7-0) to internal (Intel), so that dword writes from
host will end up little-endian in Matrox and vice versa (i.e. byte
accesses are not same from little- and big-endian hosts, but dword
accesses (recomended and only usable) are OK).
But this byte swapping done on PPC readl (if APUS not defined) causes
troubles to me. I have now some "success" reports from PPC
peoples and "unsuccessful" from Alpha and I think that after I change
it to writel, I'll get "sucess" from Alpha and unsuccess from PPC :-( )
So is there portable way to access PCI address space without
byte swapping (leave possible byte swapping on host<->PCI bridge).
Or should I do:
#ifdef __alpha__ (or #ifndef __ppc__ ??)
#define matrox_readl(x) readl(x)
#define matrox_readl(x) (*(u_int32_t*)x)
(is there something like that in headers? I did not found any.)
(except that ia32 readl adds unnecessary (x | PAGE_OFFSET) from __io_virt
which is a) incorrect for PAGE_OFFSET != 0xC0000000 (for example for
0x70000000) and b) causes register reload in sequence of readl/writel,
so it is sloooow) (+33% memory accesses in critical code path (drawing
And if asm-ppc swaps bytes on writew/l, what happens to data passed
to memcpy_toio? I hope that they are passed as-is, preferrably with
dword (or qword) data size...
And last question, is it possible (on some architectures (PPC)) that PCI
device is assigned by OpenFirmware to address 0?
Thanks and sorry for long letter, I'm a bit frustrated,
P.S.: Please, cc-me (if possible), I read digest only.
P.P.S.: Excuse my english, I'm working on it.
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