Good idea, but then we would need to distinguish between "capabilities"
and "incapabilities" (we should assume buggy TSC if _any_ CPU has broken
TSC, but assume MMX instructions if _all_ CPU's have MMX instructions).
What about negating all the bug bits? (I.e., having a "working TSC" flag
instead of "buggy TSC" flag.)
Have a nice fortnight
-- Martin `MJ' Mares <firstname.lastname@example.org> http://atrey.karlin.mff.cuni.cz/~mj/ Faculty of Math and Physics, Charles University, Prague, Czech Rep., Earth "A sine curve goes off to infinity or at least the end of the blackboard."
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