Alan Cox wrote:
> > IMHO this is a trade-off. If one wants to have the processor dissipating
> > < 150mW when Linux is idle, one has to power down the 200MHz or so
> > 64-bit TSC counter circuitry.
> The Centaur doesnt have this bug and still has a low power mode. They do
> it right. So it is a bug in the Cyrix chip.
The Centaur C6, just like the Intel CPUs, enters a low power mode when
the CPU executes a HALT instruction (i.e. when Linux is idle). However,
it is not the same low power mode as found in the Cyrix 6x86 CPUs.
Just like the Intel and the AMD K5/K6 chips, the Centaur C6 will still
dissipate around 2.5 Watts in this low power mode.
OTOH when the clock is _stopped_ (e.g. APM), the Centaur, just like the
Intel and the AMD K5/K6, will dissipate around 350 mW. However, coming
out of a clock stop condition is expensive in terms of clock cycles,
because the CPU internal clock PLL must re-synchronize with the external
The Cyrix 6x86 is unique in its ability to power down when Halted and
wake up again without a single CPU clock cycle loss.
(Context) switching to another subject: I already emailed Centaur about
the workaround, and also asked about a sample CPU for Linux testing, but
didn't get an answer yet. You mentionned you wanted to try some
optimizations for the C6.
I have a question. The 6x86MX allows one to lock L1 cache lines. Would
it be interesting to group some kernel variables and keep them in the L1
cache? Would that increase the kernel performance during context
Please give me a hint of which data structures could be kept in the L1
cache, and their size.
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