Re: [PATCH] peci: aspeed: Clear clock_divider value before setting it

[Andrew Jeffery]

On Thu, 2024-04-18 at 13:41 +0000, Winiarska, Iwona wrote:
> On Thu, 2024-04-18 at 09:11 +0930, Andrew Jeffery wrote:
> > Hi Iwona,
> > 
> > On Wed, 2024-04-17 at 15:48 +0200, Iwona Winiarska wrote:
> > > PECI clock divider is programmed on 10:8 bits of PECI Control register.
> > > Before setting a new value, clear bits read from hardware.
> > > 
> > > Signed-off-by: Iwona Winiarska <iwona.winiarska@xxxxxxxxx>
> > 
> > I think it would be best to add a Fixes: tag and Cc: stable in
> > accordance with the stable tree rules. Are you happy to do so?
> 
> Hi!
> 
> Technically, the initial value of this register should be 0, but I've added the
> clear just to be on the safe side and to not have to rely on that.

Yeah, it could cause havoc with an unbind/bind sequence if people are
messing with the clocks in between.

> I don't think we're ever programming invalid values in the real-world scenarios,
> and because of that - I don't think this is stable material.

Right, I don't expect people are doing the above in environments where
stability is a concern.

Thanks for elaborating.

Andrew