Re: [PATCH 2/2] x86/barrier: Do not serialize MSR accesses on AMD

[Borislav Petkov]

On Fri, Oct 27, 2023 at 09:09:05PM +0100, Andrew Cooper wrote:
> There are other non-serialising MSRs on AMD CPUs, including the FS/GS
> base MSRs on more modern parts which is enumerated in 8000_0021.eax[1].
> 
> So there isn't a boolean "MSRs need fencing, yes/no". 

Well, I was implying that "MSRs need fencing" refers to this particular
use case where weak_wrmsr_fence() is used - IA32_TSC_DEADLINE and X2APIC
MSRs.

So the feature bit should be named something more specific:

	X86_FEATURE_APIC_TSC_MSRS_NEED_FENCING

or so.

If we have to do something for the other case, yes, we will have to
either generalize this or add yet another flag.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette