Re: [PATCH v6 1/3] x86/fpu: Measure the Latency of XSAVES and XRSTORS

[Yi Sun]

On 07.09.2023 00:02, Ingo Molnar wrote:
> * Dave Hansen <dave.hansen@xxxxxxxxx> wrote:
>
> > On 9/6/23 02:18, Yi Sun wrote:
> > > Or just use PT
> >
> > I'd really like to be able to use this mechanism across a wide range of
> > systems over time and vendors.  For instance, if Intel's AVX512 XSAVE
> > implementation is much faster than AMD's, it would be nice to show some
> > apples-to-apples data to motivate AMD to do better.  We can't do that
> > with PT.
>
> Ack - and with the explicit tooling support, it's also very easy to provide
> such numbers.
>
> As long as the regular FPU code paths do not get new tracing overhead
> added, this looks like a useful tool.
>
> Thanks,
>
> 	Ingo
Hi Ingo and Dave,
We have been running the tool since kernel v5.19, and the patch set has
been tested in our internal repository for several months.
Additionally, we have implemented a test suite of micro-benchmark in user
space that works with this kernel trace, and it will be open-sourced soon.
With all these tools, we have obtained useful data, and we haven't
encountered any issues.

It would be great for the quality of X86 SIMD instructions if the patch
could catch up kernel v6.6.

Thanks
  --Sun, Yi