Re: [PATCH v2 5/5] phy: qcom-qmp-usb: Add Qualcomm SDX75 USB3 PHY support

[Rohit Agarwal]

On 9/6/2023 2:08 AM, Dmitry Baryshkov wrote:
> On 05/09/2023 13:30, Rohit Agarwal wrote:
> > Add support for USB3 QMP PHY found in SDX75 platform.
> >
> > Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx>
> > ---
> >   drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 158 
> > ++++++++++++++++++++++++++++++++
> >   1 file changed, 158 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c 
> > b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > index 0130bb8..57b8b5b 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > @@ -23,6 +23,7 @@
> >   #include "phy-qcom-qmp-pcs-misc-v3.h"
> >   #include "phy-qcom-qmp-pcs-usb-v4.h"
> >   #include "phy-qcom-qmp-pcs-usb-v5.h"
> > +#include "phy-qcom-qmp-pcs-usb-v6.h"
> >     /* QPHY_SW_RESET bit */
> >   #define SW_RESET                BIT(0)
> > @@ -858,6 +859,134 @@ static const struct qmp_phy_init_tbl 
> > sdx65_usb3_uniphy_rx_tbl[] = {
>
> [skipped the tables]
>
> > @@ -1556,6 +1685,32 @@ static const struct qmp_phy_cfg 
> > sdx65_usb3_uniphy_cfg = {
> >       .has_pwrdn_delay    = true,
> >   };
> >   +static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {
> > +    .lanes            = 1,
> > +    .offsets        = &qmp_usb_offsets_v5,
>
> v6?
Since the offsets for v5 and v6 are same, I did not introduce a new 
struct with the same values.
Please correct me if I have to introduce v6 offsets.
> > +
> > +    .serdes_tbl        = sdx75_usb3_uniphy_serdes_tbl,
> > +    .serdes_tbl_num        = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl),
> > +    .tx_tbl            = sdx75_usb3_uniphy_tx_tbl,
> > +    .tx_tbl_num        = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl),
> > +    .rx_tbl            = sdx75_usb3_uniphy_rx_tbl,
> > +    .rx_tbl_num        = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl),
> > +    .pcs_tbl        = sdx75_usb3_uniphy_pcs_tbl,
> > +    .pcs_tbl_num        = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl),
> > +    .pcs_usb_tbl        = sdx75_usb3_uniphy_pcs_usb_tbl,
> > +    .pcs_usb_tbl_num    = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl),
> > +    .clk_list        = qmp_v4_sdx55_usbphy_clk_l,
> > +    .num_clks        = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
> > +    .reset_list        = msm8996_usb3phy_reset_l,
> > +    .num_resets        = ARRAY_SIZE(msm8996_usb3phy_reset_l),
>
> Clocks and resets are gone in 
> https://lore.kernel.org/linux-phy/20230824211952.1397699-1-dmitry.baryshkov@xxxxxxxxxx/
Sure.
> > +    .vreg_list        = qmp_phy_vreg_l,
> > +    .num_vregs        = ARRAY_SIZE(qmp_phy_vreg_l),
> > +    .regs            = qmp_v5_usb3phy_regs_layout,
>
> This must be v6, if the rest of the PHY is using v6 register names.
Same, Shall I introduce v6 struct?

Thanks,
Rohit.
> > +    .pcs_usb_offset        = 0x1000,
> > +
> > +    .has_pwrdn_delay    = true,
> > +};
> > +
> >   static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
> >       .lanes            = 1,
> >   @@ -2256,6 +2411,9 @@ static const struct of_device_id 
> > qmp_usb_of_match_table[] = {
> >           .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
> >           .data = &sdx65_usb3_uniphy_cfg,
> >       }, {
> > +        .compatible = "qcom,sdx75-qmp-usb3-uni-phy",
> > +        .data = &sdx75_usb3_uniphy_cfg,
> > +    }, {
> >           .compatible = "qcom,sm6115-qmp-usb3-phy",
> >           .data = &qcm2290_usb3phy_cfg,
> >       }, {