Re: [PATCH V2] clk: qcom: clk-alpha-pll: Use determine_rate instead of round_rate

[Stephen Boyd]

Quoting Devi Priya (2023-09-01 00:00:41)
> The round_rate() API returns a long value as the errors are reported using
> negative error codes. This leads to long overflow when the clock rate
> exceeds 2GHz.As the clock controller treats the clock rate above signed
> long max as an error, use determine_rate in place of round_rate as the
> determine_rate API does not possess such limitations.

Does this fix something, or is it preparing for PLLs that run faster
than 2GHz?

> 
> Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx>
> ---
>  Changes in V2:
>         - Updated divider_round_rate to divider_determine_rate as 
>           suggested by Stephen Boyd.
> 
>  drivers/clk/qcom/clk-alpha-pll.c | 125 +++++++++++++++++--------------
>  1 file changed, 68 insertions(+), 57 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 1c2a72840cd2..de2b7e2784ec 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -2353,22 +2362,24 @@ static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
>         return parent_rate * l;
>  }
>  
> -static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> -                                         unsigned long *prate)
> +static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw,
> +                                            struct clk_rate_request *req)
>  {
>         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
>         unsigned long min_freq, max_freq;
>         u32 l;
>         u64 a;
>  
> -       rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
> -       if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
> -               return rate;
> +       req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
> +                                        &l, &a, 0);
> +       if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
> +               return 0;
>  
>         min_freq = pll->vco_table[0].min_freq;
>         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
>  
> -       return clamp(rate, min_freq, max_freq);
> +       req->rate = clamp(req->rate, min_freq, max_freq);
> +       return 0;
>  }

Is this any different from clk_alpha_pll_determine_rate()? I think the
only difference is alpha_pll_width, which could probably be some
argument passed to an alpha_pll_determine_rate() function that does the
internal clamping. It could also take a struct clk_rate_request then so
that we don't pass individual members of that struct.