RE: [PATCH v4 03/12] ARM: EXYNOS: remove system mmu initializationfrom exynos tree

[Cho KyongHo]

> -----Original Message-----
> From: Cho KyongHo [mailto:pullip.cho@xxxxxxxxxxx]
> Sent: Thursday, November 22, 2012 8:33 PM
> 
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index a86e88e..13d0ed6 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -24,7 +24,6 @@
> 
>  #include <mach/map.h>
>  #include <mach/regs-clock.h>
> -#include <mach/sysmmu.h>
> 
>  #include "common.h"
> 
> @@ -862,86 +861,91 @@ static struct clk exynos5_init_clocks_off[] = {
>  		.enable		= exynos5_clk_ip_gscl_ctrl,
>  		.ctrlbit	= (1 << 3),
>  	}, {
> -		.name		= SYSMMU_CLOCK_NAME,
> -		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> +		.name		= "sysmmu",
> +		.devname	= "exynos-sysmmu.0",
>  		.enable		= &exynos5_clk_ip_mfc_ctrl,
>  		.ops		= &exynos5_gate_clk_ops,
>  		.ctrlbit	= (1 << 1),
>  	}, {
> -		.name		= SYSMMU_CLOCK_NAME,
> -		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
> +		.name		= "sysmmu",
> +		.devname	= "exynos-sysmmu.1",
>  		.enable		= &exynos5_clk_ip_mfc_ctrl,
>  		.ops		= &exynos5_gate_clk_ops,
>  		.ctrlbit	= (1 << 2),
>  	}, {


Control bits for clock gating of System MMU MFC L/R is inversed in clock-exynos5.c
The following patch is the fix of the problem for 03/12 patch.

Thanks to Prathyush.

Cho KyongHo.