On Mon, May 22, 2000, Donald Becker <email@example.com> wrote:
; > ;
; > ; The very old code used eeprom_delay(100), which mean 100ns, *not* 100usec.
; > If I greep the driver that was in 2.2.6 kernel I get
; > #define eeprom_delay(nanosec) udelay(1);
; > eprom_delay(100);
; > eprom_delay(150);
; > So the "nanosec" parameter gets trashed and you delay
; > for 1 us in all of the cases.
; Well, there isn't a nanodelay(nsec) function.
; And, as you know, udelay() isn't reliable on some kernel versions.
; The usual maximum clock rate is 2.5Mhz or 4Mhz.
; That's 250 or 400ns per cycle, or 125/200ns per half cycle.
; A 33Mhz PCI bus transaction will take a minimum of 120ns, likely more.
OK now it's all clear where does the confucsion come from,
the specs that I have define a bit higher delays...
Now I understand that eeprom_delay(150) was more of a reminder
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